Translation Lookaside Buffer (TLB)

Definition & Purpose
- The TLB is a small, fast cache in the MMU (Memory Management Unit) that holds a subset of recent page‐table entries.
- It speeds up virtual‐to‐physical address translation by avoiding a full page‐table lookup in main memory on each memory reference.

Structure of a TLB Entry

Field	Description
Virtual Page Number (VPN)	High‐order bits of the virtual address
Frame Number (PFN)	Corresponding physical frame number
Valid Bit	Indicates if the entry is valid/cacheable
Protection Bits	Read/Write/Execute permissions
(Optional) Reference & Dirty Bits	For replacement and write‐back logging

Operation (Lookup Process)
1. TLB Lookup: On each memory access, the MMU extracts the VPN and checks the TLB in parallel with the cache tag check.
2. TLB Hit: If an entry with matching VPN & valid bit=1 is found, the PFN is retrieved immediately, forming the physical address.
3. TLB Miss: If no matching entry exists, the hardware or OS walks the full page table in memory to find the PFN, loads that mapping into the TLB (possibly evicting another entry), then retries the access.
Replacement & Consistency
- Replacement Policies: Often LRU or a hardware‐friendly approximation (e.g., CLOCK).
- Consistency: On a context switch or when a page‐table entry changes (e.g., on a page fault), the OS must invalidate or flush stale TLB entries (via an “invalidation” or full flush).
Advantages & Impact
- Low Latency: TLB hits are typically on the order of a single cycle, versus tens of cycles for a full page‐table walk.
- High Hit Rate: Locality of reference in programs leads to very high TLB‐hit ratios (\~90–99%), dramatically reducing average memory‐access time.